1. Technical Field
The present invention generally relates to an apparatus for performing arithmetic operations, and more particularly, to reducing noise production and power consumption by performing the addition of PKG recoded numbers.
2. Description of Related Art
Generally, traditional dual-rail encoding (i.e. mousetrap logic) is often implemented in arithmetic circuitry. Dual-rail encoding requires that multiple wires be enabled to indicate the proper value. For power and noise reasons, it is desirable to reduce the number of wires routed over an integrated circuit and the switching activity of these wires. Therefore, PKG recoding can be implemented to reduce the number of wires and the switching activity of these wires.
Illustrated in FIG. 1 is a recoding table 2 illustrating the encoding of two logical values into mousetrap logic. The mousetrap logic values are then encoded into PKG recoding values to reduce the number of wires routed over an integrated circuit from 4 wires to 3 wires. There is also a large savings in the switching activity of these wires. The switching activity is reduced from 2 of 4 wires switched to 1 of 3 wires switched, as shown by recoding table 2. These reductions cause the significant savings of cutting power consumption by 50% and the area for wiring by 25%.
Illustrated in FIG. 2A is a block diagram representing the dual rail pairs of signals for values A 3(A&B) and B 4(A&B) being recoded into PKG signals (101–103) by recoding device 9.
Illustrated in FIG. 2B is a block diagram of a possible example of a mousetrap logic encoding circuit 11 for P-propagate code in a PKG recoding. As shown in FIG. 2B, the propagate code 101 is generated from the mousetrap encoding by taking the logical “AND” operation of the high A 3B mousetrap encoded signal and the low B 4A mousetrap encoded signal in the “AND” logic 12. The output from the “AND” logic 12, is one input into the “OR” logic 14. The logical “AND” of the low A 3A mousetrap encoded sign and the high B 4B mousetrap encoded signal is performed in the “ADD” logic 13, and is input as the second input into “OR” gate 14. The final logical operation utilizing the “OR” 14 produces the P-propagate code 101 that is equal to the logical end of the A high 3B and B low 4A, or the A low 3A and B high 4B signals.
Illustrated in FIG. 2C is a block diagram of a possible example of a mousetrap logic encoding circuit 16 for K-kill code 102 in PKG recoding. The kill or clear all bits code in the PKG recoding is represented by a logical “AND” of the A low 3A and B low 4A mousetrap encoding bits. If both the A low 3A and B low 4A bits are enabled, the PKG recoding generates a K code 102, indicating the clearing of both logical bits A 4 and B 5.
Illustrated in FIG. 2D is a block diagram of a possible example of a mousetrap logic encoding circuit 18 for the G-generate code 103 in PKG recoding. The G-generate code 103 in PKG recoding, is constructed utilizing a logical end of the A high 3B and B high 4B bits in mousetrap encoding. If the A high 3B and B high 4B bits are enabled, the PKG recoding will generate a G code 103 that indicates the setting of both bits.
While using PKG recoded signals can reduce the number of wires needed to represent two values, it does cause the problem of how to add numbers in this PKG recoded form. Thus, a heretofore-unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.